In response to a growing demand for electrically erasable and programmable semiconductor memory devices that can operate without having to refresh retained data, there is a need for enhancing the storage capacity and integration density of such memory devices.
Flash memories are known for being capable of offering large capacity and high integration density without reliance on refreshing functions. Because of their ability to retain data, even when there is no supplied power, flash memory devices are widely used in many kinds of electronic devices, especially devices that may be prone to experiencing frequent interruptions in power.
FIG. 1 is a sectional diagram of a generic flash memory cell 100 that includes a source 120 and a drain 130, which are formed with a channel region interposed therebetween in a P-type semiconductor substrate 110. The flash memory cell 100 also includes a floating gate 140 that is formed by an insulation film interposed with the channel region, and a control gate 150 that is formed by an insulation film interposed with the floating gate 140.
The source 120, the drain 130, the control gate 150, and the semiconductor substrate 110 are coupled to voltage terminals Vs, Vd, Vg, and Vb, respectively, for applying voltages thereto in operations such as programming, erasing, and reading.
For example, during a programming operation, a program voltage (15V˜20V) is applied to the control gate 150 of a selected flash memory cell, while a pass voltage (about 10V) lower than the program voltage is applied to an unselected flash memory cell. Under this bias condition, electrons are injected into the floating gate due to a Fowler-Nordheim (F-N) tunneling effect. If electrons are accumulated in the floating gate, a threshold voltage of the flash memory cell is elevated. By varying a threshold voltage of the flash memory cell, data can be stored in the flash memory cell.
When a selection voltage (Vselect) is applied to the control gate 150 of the flash memory cell 100, data stored in the flash memory cell 100 is detected according to whether a cell transistor of the memory cell is turned on or off. For instance, if a memory cell transistor is turned on when a selection voltage is applied to the control gate 150 of the flash memory cell 100, the flash memory cell 100 is deemed not programmed. In contrast, if a memory cell transistor is turned on when a selective voltage is applied to the control gate 150 of the flash memory cell 100, the flash memory cell 100 is deemed programmed. In this way, a reading operation can be carried out. For example, control gates of unselected memory cell transistors are supplied with a read voltage (i.e., unselective read voltage Vread).
Programming of the flash memory cell 100 is not complete until a threshold voltage of the memory cell rises up sufficiently by injection of electrons into the floating gate 140. Thus, a reading verification operation is needed to determine whether enough electrons are accumulated in the floating gate 140 to raise the threshold voltage of the flash memory cell 100.
As such, reading and reading verification operations are required for the flash memory cell 100. Described below is a typical reading operation of the flash memory device 100. Such a reading operation generally includes a generic reading operation or a reading verification operation for program verification.
During reading and reading verification operations, however, a channel voltage of the flash memory cell 100 can rise to an undesired level by a bias condition with string and ground selection lines SSL and GSL and selected and unselected word lines, as shown in FIG. 3. Referring to FIG. 3, if a memory cell Mk coupled to a selected word line WLk has been programmed, a channel voltage between the string selection line SSL and the selected word line WLk becomes a biased level of the corresponding bit line while a channel voltage between the word line WLk and the ground selection line GSL increases by the unselected read voltage (Vread) that is applied to the unselected word lines (channel boosting). Such an increased channel voltage induces a voltage difference between the upper and lower channels on the selected word line WLk. This voltage difference generates a leakage current through the memory cell Mk toward the string selection line SSL from the ground selection line GSL. This leakage current can inadvertently program an unselected memory cell by a hot-electron injection effect, which is referred to as ‘read disturbance.’ Such read disturbance should be blocked therefrom for the purpose of improving the reliability of the flash memory device.